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The Power Wall – Are We Scaling it, or is it Just Getting Higher?

At a plenary panel at ISSCC 2011, a number of leaders in the technology and circuit design arenas offered their perspective on how to accomplish a factor of 10x in power reduction over the next 5 years. No clear breakthrough solutions were ventured. Technology solutions such as FD-SOI combined with continued voltage scaling, concurrency and heterogeneity may ultimately result in a factor 10 if one works very hard. It is clear that larger reductions, sorely needed from an application as well as an environmental perspective, will require more innovative solutions. In this presentation, we will analyze a number of approaches that have the potential of doing so. More specifically, they remove the layers of inefficiency that still exist in most system implementations my gradually removing the margins – even to the point of designs operating with negative margins. This approach shifts the tasks of verification and validation from design-time to run-time, requiring systems that dynamically adapt to chances in the environment as well as the processing requirements. The talk will conclude with some speculation on ways of getting closer to the ultimate energy-bounds, such as neuro-inspired computing. Biography – Jan M. Rabaey Site: Jan Rabaey received his Ph.D degree in applied sciences from the Katholieke Universiteit Leuven, Belgium. After being connected to UC Berkeley as a Visiting Research Engineer, he was a research manager at IMEC, Belgium. In 1987, he joined the faculty of the Electrical Engineering and Computer Science department of the University of California, Berkeley, where he now holds the Donald O. Pederson Distinguished Professorship. He is currently the scientific co-director of the Berkeley Wireless Research Center (BWRC), as well as the director of the Berkeley Ubiquitous SwarmLab and the multi-university Multiscale Systems Research Center (MuSyC). He is the recipient of a wide range of awards, amongst which the IEEE CAS Society Mac Van Valkenburg Award, the European Design Automation Association (EDAA) Lifetime Achievement award, and the Semiconductor Industry Association (SIA) University Researcher Award. He is an IEEE Fellow and a member of the Royal Flemish Academy of Sciences and Arts of Belgium. In 2012, he received an honorary doctorate from the University of Lund, Sweden. His research interests include the conception and implementation of next-generation integrated wireless systems.